 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| ISPPAC-POWR1208P1 In-System Programmable Power Supply Sequencing Controller and Precision Monitor February 2005 Data Sheet DS1033 (R) Features Monitor and Control Multiple Power Supplies * * * * Simultaneously monitors up to 12 power supplies Sequence controller for power-up conditions Provides eight output control signals Programmable digital and analog circuitry Application Block Diagram Primary + DC/DC + Supply Gnd +5V RG +3.3V Primary + + DC/DC Supply Gnd RG +2.5V RG + + DC/DC Supply Gnd +1.0V RG 12 Analog Inputs 10uF VDD VDDINP VMON1 HVOUT1 VMON2 HVOUT2 VMON3 HVOUT3 VMON4 HVOUT4 VMON5 OUT5 VMON6 ISPPAC-POWR1208P1 OUT6 VMON7 OUT7 VMON8 OUT8 Power Sequence VMON9 Comp1 Controller VMON10 Comp2 VMON11 Comp3 VMON12 Comp4 0.1uF OE/EN +5V Circuits +3.3V Circuits Precision Analog Comparators for Monitoring * 12 analog comparators for monitoring * 384 programmable threshold levels spanning 0.68V to 5.93V * 0.5% precision * Other user-defined voltages possible * 80mV near-ground threshold for power-off detect * Each comparator independently configurable * Eight direct comparator outputs * Digital filter on comparator outputs Primary + - + DC/DC Supply Gnd +2.5V Circuits +1V Circuits Primary DC/DC Supply or Regulator OE/EN VDD DC/DC Supply or Regulator 3.3V Embedded PLD for Sequence Control * Implements state machine and input conditional events * In-System Programmable (ISPTM) through JTAG and on-chip E2CMOS(R) * Input synchronizers CLK RESET IN1 IN2 IN3 IN4 Comp5 Comp6 Comp7 Comp8 POR CREF 0.1uF EN 3.3V Digital Logic EN Digital Logic Embedded Programmable Timers * 4 Programmable 8-bit timers (32s to 524ms) * Programmable time delay between multiple power supply ramp-up and wait statements Description The Lattice ISPPAC-POWR1208P1 incorporates both insystem programmable logic and in-system programmable analog circuits to perform special functions for power supply sequencing and monitoring. The ispPACPOWR1208P1 device has the capability to be configured through software to control up to eight outputs for power supply sequencing and 12 comparators monitoring supply voltage limits, along with four digital inputs for interfacing to other control circuits or digital logic. Once configured, the design is downloaded into the device through a standard JTAG interface. The circuit configuration and routing are stored in non-volatile E2CMOS. PAC-Designer,(R) an easy-to-use Windows-compatible software package gives users the ability to design and simulate logic and sequences that control the power supplies or FET driver circuits. The user has control over timing functions, programmable logic functions and comparator threshold values as well as I/O configurations. Embedded Oscillator * * * * Built-in clock generator, 1MHz Programmable clock frequency Programmable timer pre-scaler External clock support Programmable Output Configurations * Four digital outputs for logic and power supply control * Four fully programmable gate driver outputs for FET control, or programmable as four additional digital outputs * Expandable with ispMACHTM 4000 CPLD 2.7V to 5.5V Supply Range * In-system programmable at 3.0V to 5.5V * Industrial temperature range: -40C to +85C * 44-pin TQFP package (c) 2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 3-1 DS1033_01.0 Lattice Semiconductor ISPPAC-POWR1208P1 Data Sheet Power Supply Sequence Controller and Monitor The ISPPAC-POWR1208P1 device is specifically designed as a fully-programmable power supply sequencing controller and monitor for managing up to eight separate power supplies, as well as monitoring up to 12 analog inputs or supplies. The ISPPAC-POWR1208P1 device contains an internal PLD that is programmable by the user to implement digital logic functions and control state machines. The internal PLD connects to four programmable timers, special purpose I/O and the programmable monitoring circuit blocks. The internal PLD and timers can be clocked by either an internal programmable clock oscillator or an external clock source. The voltage monitors are arranged as 12 independent comparators, each with 384 programmable trip-point settings ranging from 0.68V to 5.392V in roughly 0.5% steps. An additional low-voltage threshold (80mV) is also provided for sensing power-off conditions. The voltage monitors incorporate two features designed to increase their robustness. The first is a small amount of hysteresis. In general, more hysteresis implies more noise immunity, but as trip-points decrease a fixed amount of hysteresis would adversely affect the trip-point accuracy. For this reason the ISPPAC-POWR1208P1's voltage monitors use a scheme in which hysteresis scales with trip-point voltages remaining at a nearly constant 0.5% of the selected trip-point. Hysteresis is 30mV for a 5.932V trip-point and scales down to 4mV for a 0.68V trip-point. The second feature that increases the voltage monitor's robustness are a synchronizer and digital filter in each monitor circuit. The filter may be optionally enabled to provide higher noise immunity at the cost of a somewhat increased response time. The programmable logic functions consist of a block of 36 inputs with 81 product terms and 16 macrocells. The architecture supports the steering of product terms to enhance the overall usability. Output pins are configurable in two different modes. There are eight outputs for controlling eight different power supplies. OUT5-OUT8 are open-drain outputs for interfacing to other circuits. The HVOUT1-HVOUT4 pins can be programmed individually as open-drain outputs or as high voltage FET gate drivers. As high voltage FET gate driver outputs, they can be used to drive an external N-Channel MOSFET as a switch to control the voltage rampup of the target board. The four HVOUT drivers have programmable current and voltage levels. Figure 3-1. ISPPAC-POWR1208P1 Block Diagram ISPPAC-POWR1208P1 VMON1 VMON2 VMON3 VMON4 VMON5 VMON6 VMON7 VMON8 VMON9 VMON10 VMON11 VMON12 8 Analog Inputs 12 Sequence Controller CPLD 4 Comparator Outputs COMP1 COMP2 COMP3 COMP4 COMP5 COMP6 COMP7 COMP8 VDD HVOUT1 HVOUT2 HVOUT3 HVOUT4 36 I/P & 16 Macrocell GLB 5 High Voltage Outputs 4 IN1 IN2 IN3 IN4 RESET Digital Inputs 250kHz Internal OSC 4 Timers Logic Outputs OUT5 OUT6 OUT7 OUT8 CLKIO 3-2 Lattice Semiconductor ISPPAC-POWR1208P1 Data Sheet Pin Descriptions Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Name HVOUT4 HVOUT3 HVOUT2 HVOUT1 VDD IN1 IN2 IN3 IN4 RESET VDDINP OUT5 OUT6 OUT7 OUT8 COMP8 COMP7 COMP6 COMP5 COMP4 COMP3 COMP2 COMP1 TCK POR CLK GND TDO TRST TDI TMS VMON1 VMON2 VMON3 VMON4 VMON5 VMON6 VMON7 Pin Type O/D Output Current Source O/D Output Current Source O/D Output Current Source O/D Output Current Source Power CMOS Input CMOS Input CMOS Input CMOS Input CMOS input1 Power2 O/D Output O/D Output O/D Output O/D Output O/D Output O/D Output O/D Output O/D Output O/D Output O/D Output O/D Output O/D Output TTL/LVCMOS Input O/D Output Bi-directional I/O3 Ground TTL/LVCMOS Output TTL/LVCMOS Input TTL/LVCMOS Input TTL/LVCMOS Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Open-drain Output 4 FET Gate Driver 4 Open-drain Output 3 FET Gate Driver 3 Open-drain Output 2 FET Gate Driver 2 Open-drain Output 1 FET Gate Driver 1 Main Power Supply Input 1, Schmitt-Trigger Input Input 2, Schmitt-Trigger Input Input 3, Schmitt-Trigger Input Input 4, Schmitt-Trigger Input PLD Reset Input, Active Low, Schmitt-Trigger Input Digital Inputs Power Supply Open-Drain Output Open-Drain Output Open-Drain Output Open-Drain Output VMON8 Comparator Output (Open-Drain) VMON7 Comparator Output (Open-Drain) VMON6 Comparator Output (Open-Drain) VMON5 Comparator Output (Open-Drain) VMON4 Comparator Output (Open-Drain) VMON3 Comparator Output (Open-Drain) VMON2 Comparator Output (Open-Drain) VMON1 Comparator Output (Open-Drain) Test Clock (JTAG Pin) Power-On-Reset Output Clock Output (Open-Drain) or Clock Input Ground Test Data Out (JTAG Pin) Test Reset, Active Low, 50k Ohm Internal Pull-up (JTAG Pin, Optional Use) Test Data In, 50k Ohm Internal Pull-up (JTAG Pin) Test Mode Select, 50k Ohm Internal pull-up (JTAG Pin) Voltage Monitor Input 1 Voltage Monitor Input 2 Voltage Monitor Input 3 Voltage Monitor Input 4 Voltage Monitor Input 5 Voltage Monitor Input 6 Voltage Monitor Input 7 Description 3-3 Lattice Semiconductor ISPPAC-POWR1208P1 Data Sheet Pin Descriptions (Continued) Number 39 40 41 42 43 44 Name CREF VMON8 VMON9 VMON10 VMON11 VMON12 Pin Type Reference 4 Description Reference for Internal Use, Decoupling Capacitor (.1uf Required, CREF to GND) Voltage Monitor Input 8 Voltage Monitor Input 9 Voltage Monitor Input 10 Voltage Monitor Input 11 Voltage Monitor Input 12 Analog Input Analog Input Analog Input Analog Input Analog Input 1. RESET is an active low INPUT pin, external pull-up resistor to VDD is required. When driven low it resets all internal PLD flip-flops to zero, and may turn "ON" or "OFF" the output pins, including the HVOUT pins depending on the polarity configuration of the outputs in the PLD. If a reset function is needed for the other devices on the board, the PLD inputs and outputs can be used to generate these signals. The RESET should be used if multiple ISPPAC-POWR1208P1 devices are cascaded together in expansion mode. 2. VDDINP can be chosen independent of VDD. It is used to set the logic threshold only to the four logic inputs IN1-IN4. 3. CLK is the PLD clock output in master mode. It is re-routed as an input in slave mode. The clock mode is set in software during design time. In output mode it is an open-drain type pin and requires an external pull-up resistor. Multiple ISPPAC-POWR1208P1 devices can be tied together with one acting as the master, the master can use the internal clock and the slave can be clocked by the master. The slave needs to be set up using the clock as an input. 4. The CREF pin requires a 0.1F capacitor to ground, near the device pin. This reference is used internally by the device. No additional external circuitry should be connected to this pin. Absolute Maximum Ratings Absolute maximum ratings are shown in the table below. Stresses beyond these listed values may cause permanent damage to the device. Functional operation of the device at these or any other conditions outside those indicated in the operating sections of this specification is not implied. Symbol VDD VDDINP VIN2 VMON VTRI TS TA TSOL 1 Parameter Core supply voltage at pin Digital input supply voltage for IN1-IN4 Input voltage applied, digital inputs Input voltage applied, VMON voltage monitor inputs Tristated or open drain output, external voltage applied (CLK pin 26 pull-up VDD). Storage temperature Ambient temperature with power applied Maximum soldering temperature (10 sec. at 1/16 in.) Conditions -- -- -- -- -- -- -- -- -- Min. -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -65 -55 -- Max. 6.0 6.0 15 6.0 7.0 6.0 150 125 260 Units V V V V V V C C C HVOUTmax HVOUT pin voltage, max = VDD + 9V 1. VDDINP is the supply pin that controls logic inputs IN1-IN4 only. Place 0.1F capacitor to ground and supply the V DDINP pin with appropriate supply voltage for the given input logic range. 2. Digital inputs are tolerant up to 5.5V, independent of the VDDINP voltage. 3-4 Lattice Semiconductor ISPPAC-POWR1208P1 Data Sheet Recommended Operating Conditions Symbol VDD VDDPROG VDDINP1 VIN 2 Parameter Core supply voltage at pin Core supply voltage at pin Digital input supply voltage for IN1-IN4 Input voltage digital inputs Voltage monitor inputs VMON1 - VMON12 2 Conditions During E cell programming Min. 2.7 3.0 2.25 0 0 Max. 5.5 5.5 5.5 5.5 6.0 -- +85 +85 Units V V V V V Cycles C C VMON Erase/Program Cycles TAPROG TA EEPROM, programmed at VDD = 3.0V to 5.5V Ambient temperature during programming Ambient temperature Power applied 1000 -40 -40 1. VDDINP is the supply pin that controls logic inputs IN1-IN4 only. Place 0.1F capacitor to ground and supply the V DDINP pin with appropriate supply voltage for the given input logic range. 2. Digital inputs are tolerant up to 5.5V, independent of the VDDINP voltage. Analog Specifications Over Recommended Operating Conditions Symbol IDD IDDINP Parameter VDD Supply Current VDDINP Supply Current Conditions Internal Clock = 1MHz Min. -- -- Typ. 10 5 Max. 20 20 Units mA A Reference Symbol VREF 1 Parameter Reference voltage at CREF pin Conditions T = 25C Min. -- Typ. 1.16 Max. -- Units V 1. CREF pin requires a 0.1F capacitor to ground. Voltage Monitors Symbol RIN VMON Range Parameter Input impedance Programmable voltage monitor trip point (384 steps) T = 25 C, VDD = 3.3V VMON 1.8V T = 25 C, VDD = 3.3V VMON > 1.8V -40C to +85C VDD = 3.3V Conditions Min. 70 0.680 -0.5 Typ. 100 Max. 130 5.932 +0.5 Units k V % VMON Accuracy Absolute accuracy of any trip point2 -0.6 30 0.5% of trip point setting 70 80 0.07 +0.6 % ppm/ C % VMON Tempco1 VHYST VMONLO PSR Temperature drift of any trip point Hysteresis of VMON input Near-ground sense threshold Trip point sensitivity to VDD T = 25 C, VDD = 3.3V VDD = 3.3V 90 mV %/V 1. See Performance Graphs section. 2. Guaranteed by characterization. 3-5 Lattice Semiconductor ISPPAC-POWR1208P1 Data Sheet High Voltage FET Drivers Symbol VPP Range VPP Accuracy VPP Step ISOURCE Range ISOURCE Accuracy ISTEP RSINK Parameter Programmable gate driver voltage (eight steps) Absolute accuracy of VPP output voltage Gate driver voltage step Programmable ISOURCE current (32 steps) Absolute accuracy of ISOURCE current Relative current value, from any ISOURCE setting to the next Gate driver sink/discharge resistor FET Driver in OFF state when setting FET driver to a LOW state Conditions (Note 1) 25C (Note 2) Min. 8 -10 -- 0.5 -- -- -- Typ. -- -- 0.5 -- 10 15 8 Max. 12 10 -- 50 -- -- -- Units V % V A % % k 1. Maximum voltage of VPP is not to exceed 7.5V over VDD. 2. The high voltage driver outputs are set in software, HVOUT voltage range is between 8V and 12V. V DD values determine the maximum VPP. Power-On-Reset Symbol VLPOR3 VHPOR3 Parameter Conditions Min. -- -- Typ. -- -- Max. 1.15 2.1 Units V V VDD supply threshold above which POR outVDD ramping up1 put is guaranteed to be driven low VDD supply threshold above which POR output is guaranteed driven high, and device VDD ramping up1 initializes POR delay2 VDD ramping up to 3.3V in <10s CREF = 0.1F tDPOR VRESET -- 1.8 3 -- -- 2.1 ms V VDD supply threshold below which will trigger VDD ramping down1 a reset cycle from the "ON' state. 1. POR tests run with 10k resistor pulled up to VDD. 2. 1MHz clock must be present. 3. Hysteresis = 50mV. 3-6 Lattice Semiconductor ISPPAC-POWR1208P1 Data Sheet AC/Transient Characteristics Over Recommended Operating Conditions Symbol Voltage Monitors tPDMON Propagation Delay. Output transitions after a step input, from VMON to comparator output Glitch filter OFF.1 Input VTRIP + 100mV to VTRIP - 100mV Glitch filter ON.1 Input VTRIP + 100mV to VTRIP - 100mV -- 28 4 32 7 35 s s Parameter Conditions Min. Typ. Max. Units. Oscillators fCLK PLDCLKext PLDCLK Range Timers Timeout Range Range of programmable time-out duration (15 steps) (Note 1) 0.03 -- 524 ms Internal Master Clock frequency Frequency range of applied external clock source External clock applied 0.8 0.8 1.95 1 -- -- 1.2 1.2 250 MHz MHz kHz Programmable frequency range (Note 1) of PLD clock (8 binary steps) 1. Assumes 1MHz clock. Digital Specifications Over Recommended Operating Conditions Symbol IIL, IIH IPU VOL Parameter Input or I/O leakage current, no pull-up Input pull-up current (TMS, TDI, TRST) Output Low Voltage [OUT5-OUT8] [COMP1-COMP8] [HVOUT1-HVOUT4] Conditions 0V VIN VDDINP or VDD 25 C 25 C ISINKOUT = 4mA 0.4 V 70 Min. Typ. Max. +/-10 Units A A ISINKHVOUT ISINKOUT ISINKTOTAL Maximum sink current for HVOUT pins in (Note 1) open-drain mode [HVOUT1-HVOUT4] Maximum sink current for logic outputs [OUT5-OUT8], [COMP1-COMP8] Total combined sink currents from all outputs [OUT, HVOUT, COMP] (Note 1) (Note 1) 10 20 80 mA mA mA 1. [OUT5-OUT8] and [COMP1-COMP8] can sink up to 20mA max. per pin for LEDs, etc. However, output voltage levels may exceed VOL. Total combined sink currents from all outputs (OUT, HVOUT, COMP) should not exceed ISINKTOTAL. DC Input Levels: IN1-IN4 Symbol VIL VIH Parameter Schmitt trigger input low voltage Schmitt trigger input high voltage Min. -0.3 0.75 x VDDINP Max. 0.25 x VDDINP 5.5 Units V V Note: VDDINP is the input supply pin for IN1-IN4 digital logic input pins. These pins' Schmitt-Trigger thresholds are dependent on the voltage at VDDINP. 3-7 Lattice Semiconductor ISPPAC-POWR1208P1 Data Sheet Timing Characteristics Over Recommended Operating Conditions Symbol PLD Timing tPD tRST Combinatorial propagation delay from INx input to OUTx output. RESET pulse width 25 150 ns s Parameter Conditions Min. Typ. Max. Units Timing for JTAG Operations Symbol tCKMIN tCKH tCKL tMSS tMSH tDIS tDIH tDOZX tDOV tDOXZ tRSTMIN tPWP tPWE TCK high time TCK low time TMS setup time TMS hold time TDI setup time TDI hold time TDO float to valid delay TDO valid delay TDO valid to float delay Minimum reset pulse width Time for a programming operation Time for an erase operation 1 Parameter Minimum clock period Conditions Min 1 200 200 15 50 15 50 Typ. Max Units s ns ns ns ns ns ns 200 200 200 40 40 40 100 100 ns ns ns ns ms ms 1. tPWP represents programming pulse width for a single row of E2CMOS cells. tCKH tCK tMSS tMSH tCKL tCKMIN tCK tMSS tPWP, tPWE tMSS Program and Erase cycles executed in Run-Test/Idle tMS tDIS tDIH tMS tDI tDOZH tDO tDOV tDOXZ 3-8 Lattice Semiconductor ISPPAC-POWR1208P1 Data Sheet Performance Graphs Upper Trip Point Error (TP's <= 1.8V) (VCC = 3.3V, 25C) 1600 1600 Lower Trip Point Error (TP's <= 1.8V) (VCC = 3.3V, 25C) 1400 1400 1200 1200 Frequency 800 Frequency 1000 1000 800 600 400 600 400 200 200 0 0 -1 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Trip Error (%) Upper Trip Point Error (TP's > 1.8V) (VCC = 3.3V, 25C) 1200 1200 1000 1000 800 800 Frequency 600 Frequency 600 400 400 200 200 -1 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Trip Error (%) Typical Change in Trip Point vs. Temperature 0.5 0.4 Trip Point Error (%) 0.3 0.2 0.1 0 -0.1 -40 -20 0 20 40 Temperature (C) 3-9 -1 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 0 -1 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Trip Error (%) Lower Trip Point Error (TP's > 1.8V) (VCC = 3.3V, 25C) Trip Error (%) 60 80 100 Lattice Semiconductor Table3-1. VMON Trip Points 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0.680 0.684 0.688 0.692 0.696 0.700 0.704 0.708 0.712 0.716 0.720 0.724 0.728 0.732 0.736 0.740 0.744 0.748 0.752 0.756 0.760 0.764 0.768 0.772 0.776 0.780 0.784 0.787 0.791 0.795 0.799 0.803 2 0.808 0.812 0.817 0.822 0.827 0.831 0.836 0.841 0.845 0.850 0.855 0.860 0.864 0.869 0.874 0.878 0.883 0.888 0.893 0.897 0.902 0.907 0.911 0.916 0.921 0.926 0.930 0.935 0.940 0.944 0.949 0.954 3 0.962 0.968 0.974 0.979 0.985 0.990 0.996 1.002 1.007 1.013 1.019 1.024 1.030 1.035 1.041 1.047 1.052 1.058 1.064 1.069 1.075 1.081 1.086 1.092 1.097 1.103 1.109 1.114 1.120 1.126 1.131 1.137 4 1.142 1.149 1.156 1.162 1.169 1.176 1.182 1.189 1.196 1.202 1.209 1.216 1.222 1.229 1.236 1.243 1.249 1.256 1.263 1.269 1.276 1.283 1.289 1.296 1.303 1.310 1.316 1.323 1.330 1.336 1.343 1.350 5 1.363 1.371 1.378 1.386 1.394 1.402 1.410 1.418 1.426 1.434 1.442 1.450 1.458 1.466 1.474 1.482 1.490 1.498 1.506 1.514 1.522 1.530 1.538 1.546 1.554 1.562 1.570 1.578 1.586 1.594 1.602 1.610 6 1.618 1.628 1.637 1.647 1.656 1.666 1.675 1.685 1.694 1.704 1.713 1.723 1.732 1.742 1.751 1.761 1.770 1.780 1.789 1.799 1.808 1.818 1.827 1.837 1.846 1.856 1.865 1.875 1.884 1.894 1.903 1.913 7 1.931 1.942 1.954 1.965 1.976 1.988 1.999 2.010 2.021 2.033 2.044 2.055 2.067 2.078 2.089 2.101 2.112 2.123 2.135 2.146 2.157 2.169 2.180 2.191 2.203 2.214 2.225 2.237 2.248 2.259 2.271 2.282 ISPPAC-POWR1208P1 Data Sheet 8 2.289 2.302 2.316 2.329 2.342 2.356 2.369 2.383 2.396 2.410 2.423 2.437 2.450 2.464 2.477 2.490 2.504 2.517 2.531 2.544 2.558 2.571 2.585 2.598 2.612 2.625 2.638 2.652 2.665 2.679 2.692 2.706 9 2.724 2.741 2.757 2.773 2.789 2.805 2.821 2.837 2.853 2.869 2.885 2.901 2.917 2.933 2.949 2.965 2.981 2.997 3.013 3.029 3.045 3.061 3.077 3.093 3.109 3.125 3.141 3.157 3.173 3.189 3.205 3.221 10 3.241 3.260 3.279 3.298 3.318 3.337 3.356 3.375 3.394 3.413 3.432 3.451 3.470 3.489 3.508 3.527 3.547 3.566 3.585 3.604 3.623 3.642 3.661 3.680 3.699 3.718 3.737 3.756 3.776 3.795 3.814 3.833 11 4.221 4.246 4.270 4.295 4.320 4.345 4.370 4.394 4.419 4.444 4.469 4.494 4.518 4.543 4.568 4.593 4.618 4.642 4.667 4.692 4.717 4.742 4.766 4.791 4.816 4.841 4.866 4.890 4.915 4.940 4.965 4.990 12 5.017 5.046 5.076 5.105 5.135 5.164 5.194 5.224 5.253 5.283 5.312 5.342 5.371 5.401 5.430 5.460 5.489 5.519 5.548 5.578 5.607 5.637 5.666 5.696 5.726 5.755 5.785 5.814 5.844 5.873 5.903 5.932 Table 3-1 shows all possible comparator trip point voltage settings. There are 384 available voltages, ranging from 0.680V to 5.932V, as well as a `near-ground' monitor threshold of 80mV which can be used to determine if a power supply rail has completely discharged to an OFF state. In addition to these 385 voltage monitor trip points, the user can add external resistors to divide down the voltage and achieve virtually any voltage trip point. This allows the capability to monitor higher voltages such and 12V, 15V, 24V, etc. Voltage monitor trip points are set in the graphical user interface of PAC-Designer software by simple pull-down menus. The user simply selects the given range and corresponding trip point value. Attenuation and reference values are set internally using E2CMOS configuration bits internal to the device. Theory Of Operation The ISPPAC-POWR1208P1 incorporates programmable voltage monitors along with digital inputs and outputs as well as high voltage FET gate drivers to control MOSFETs for ramping up power supply rails. The 16 macrocell 3-10 Lattice Semiconductor ISPPAC-POWR1208P1 Data Sheet PLD inputs are from the 12 voltage monitors and four digital inputs. There are four embedded programmable timers that interface with the PLD, along with an internal programmable oscillator. The 12 independently programmable voltage monitors each have 384 programmable trip points over the range of 0.680V to 5.932V. Additionally, a 80mV `near-ground' sensing threshold is selectable which allows the voltage monitors to determine if a monitored signal has dropped to ground-level. This feature is especially useful for determining if a power supply's output has completely turned off. Figure 2 shows a simplified schematic representation of one of these monitors. Figure 3-2. Voltage Monitors Programmable Reference (32 selections) Monitor Voltage VMON1..VMON12 250kHz Clock D Comparator with Hysteresis Q Digital Filter Input Attenuator (12 taps) Sampling Flip-flop OFF ON To PLD Array Digital Filter ON/OFF Each monitor consists of four major subsystems. The core of the monitor is a precision voltage comparator. This comparator outputs a HIGH signal to the PLD array if the voltage at its positive terminal is greater than that at its negative terminal, otherwise it outputs a LOW signal. A small amount of hysteresis is provided by the comparator to reduce the effects of input noise. The second subsystem is a programmable resistive divider that attenuates the input signal before it is fed into the comparator. This feature is used to determine the coarse range in which the comparator should trip (e.g. 1.8V, 3.3V, 5V). Twelve possible ranges are available from the input divider network. The third subsystem is a programmable reference, which may be set to one of 32 possible values scaled in approximately 0.5% increments apart from each other, allowing for fine-tuning of the voltage monitor's trip points. One additional setting is provided to implement the 80mV `near-ground' sense setting. This combination of coarse and fine adjustment supports 384 possible trip-point voltages for a given monitor circuit, in addition to the `near-ground' sense setting. Because each monitor's reference and input divider settings are completely independent of those of the other monitor circuits, the user can set any input monitor to any of the 385 available settings. A comparator will turn on at the specified trip-point and turn off at the specified trip-point minus the hysteresis. The hysteresis provided by the voltage monitor is a function of the input divider setting and is derived from the difference in voltage between the current setting and the one immediately below it. The following table lists the typical hysteresis versus voltage monitor trip-point. 3-11 Lattice Semiconductor Table 3-2. Comparator Hysteresis vs. Setpoint Setpoint Range (V) Low Limit 5.017 4.221 3.241 2.724 2.289 1.931 1.618 1.363 1.142 0.962 0.808 0.68 80 mV High Limit 5.932 4.99 3.833 3.221 2.706 2.282 1.913 1.61 1.35 1.137 0.954 0.803 ISPPAC-POWR1208P1 Data Sheet Hysteresis (mV) 30 25 19 16 14 12 10 8 7 6 5 4 0 (disabled) The fourth subsystem in the ISPPAC-POWR1208P1's input voltage monitor is a synchronizer latch and optional digital filter. The synchronizer flip-flop samples the comparator's output state synchronously with the internal system clock. Synchronous sampling effectively eliminates the possibility of race conditions occurring in any state-controllers implemented in the ISPPAC-POWR1208P1's internal PLD logic. An optional digital filter is also provided for each comparator input for the purpose of suppressing glitches and other short transients. This filter is implemented using a saturating counter. When the comparator output is HIGH, the filter counts up to a maximum of `111', and when the comparator output is LOW the filter counts down to a minimum of `000'. When a `111' count is reached, the output of the filter is set HIGH, and when the `000' count is reached, the output is set LOW. Because the filter is clocked at the same rate as the synchronizer, the combination of the two imposes a delay of 8 sampling periods, or 32 clock cycles (32s at 1MHz). The digital filters may be enabled or disabled individually on a channel-by-channel basis by the user. PLD Architecture The ISPPAC-POWR1208P1 digital logic is composed of an internal PLD that is programmed to perform the sequencing functions. The PLD architecture allows flexibility in designing various state machines and control logic used for monitoring. The macrocell shown in Figure 3-3 is the heart of the PLD. There are 16 macrocells that can be used to control the functional states of the sequencer state machine or other control or monitoring logic. The PLD AND array shown in Figure 3-4 has 36 inputs, and 81 product terms (PTs). The resources from the AND array feed the 16 macrocells. The resources within the macrocells share routing and contain a product-term allocation array. The product term allocation array greatly expands the PLD's ability to implement complex logical functions by allowing logic to be shared between adjacent blocks and distributing the product terms to allow for wider decode functions. The basic macrocell has five product terms that feed the OR gate and the flip-flop. The flip-flop in each macrocell is independently configured. It can be programmed to function as a D-Type or T-Type flip-flop. Combinatorial functions are realized by bypassing the flip-flop. By having the polarity control XOR, the logic reduction can be best fit to minimize the number of product terms. The flip-flop's clock is driven from a common clock that can be generated from a pre-scaled, on-board clock source or from an external clock. The macrocell also supports asynchronous reset and preset functions, derived from either product terms, the global reset input or the power-on reset signal. 3-12 Lattice Semiconductor Figure 3-3. ISPPAC-POWR1208P1 Macrocell Block Diagram Global Reset Global Polarity Fuse for Init Product Term Block Init Product Term ISPPAC-POWR1208P1 Data Sheet Power On Reset Product Term Allocation PT4 PT3 PT2 PT1 PT0 R D/T P Q To ORP Polarity CLK Clock Macrocell flip-flop provides D, T, or combinatorial output with polarity 3-13 Lattice Semiconductor Figure 3-4. PLD and Timer Functional Block Diagram POR/RESET 4 PT[0..4] ISPPAC-POWR1208P1 Data Sheet 16 Logic Macrocells MC0 HVOUT1 4 PT[5..9] VMON[1..12] 12 Synchronizer 12 + Digital Filters (12) 4 PT[10..14] MC1 HVOUT2 HVOUT3 MC2 AND ARRAY IN[1..4] 4 36 Inputs 81 Product Terms 4 PT[70..74] Output Routing Pool HVOUT4 OUT5 OUT6 MC14 OUT7 OUT8 4 PT[75..79] MC15 BLK Init 16 16 4 Routing Pool Timer 1 Timer 2 Timer 3 Timer 4 Clock Generation 3-14 Lattice Semiconductor Clock and Timer Systems ISPPAC-POWR1208P1 Data Sheet Figure 3-5 shows a block diagram of the ISPPAC-POWR1208P1's internal clock and timer systems. The PLD clock can be programmed with eight different frequencies based on the internal oscillator frequency of 1MHz. Figure 3-5. Clock and Timer Block To VMON Samplers and Digital Filters Timer1 Timer2 Internal OSC 1MHz Timer Prescaler (Time Out Range) Timer3 Timer4 CLK PLD Clock Prescaler INT/EXT Select 1MHz/Prescaler Select The internal oscillator runs at a fixed frequency of 1 MHz. This signal is used as a source for the PLD clock prescaler, the timer clock prescaler, and also for synchronizing the comparator outputs and clocking the digital filters in the voltage monitor circuits. Figure 5 shows a functional block diagram of the ISPPAC-POWR1208P1's internal clock system. The ISPPAC-POWR1208P1 can operate from either its own internal or an external supplied clock source. When the device is configured to use the internal clock source (Schematically, INT/EXT select switch is in upper position), the CLK pin operates as an output. The user may select either the 1MHz internal clock, or the output of the PLD clock prescaler to be driven out of this pin (1MHz/Prescaler select switch). When the device is configured to use the external clock source (INT/EXT select switch is in lower position), the CLK pin is configured as an input, and the externally applied clock signal is routed to all prescalers, synchronizers, and other internal functions. The ISPPAC-POWR1208P1 provides prescalers to provide for flexibility in selecting the PLD clock and wide dynamic range for the timers. The frequencies available for the PLD clock will be the external clock frequency divided by the chosen prescaler value (listed in Table 3-3). 3-15 Lattice Semiconductor Table 3-3. PLD Clock Frequency (kHz) PLD Prescaler Divider1 PLD Prescaler Divider 4 8 16 32 64 128 256 512 1. Frequency values based on 1MHz clock ISPPAC-POWR1208P1 Data Sheet PLD Clock Frequency (kHz) 250 125 62.5 31.3 15.6 7.8 3.9 2.0 Because the ISPPAC-POWR1208P1's PLD array is clocked from a divided-down version of the device's 1MHz main clock, special considerations must be observed for asserting input data if it is to be reliably recognized by state machines implemented using the device. Data presented to the IN1 through IN4 digital inputs must be asserted for a minimum of at least one PLD clock period (4s - 512s depending on the PLD prescaler setting) to be recognized. For data presented to the VMON inputs, this minimum assertion time may need to be increased to account for the behavior of the VMON samplers and digital filters (when enabled). The Timer Clock Pre-Scaler divides the internal 1MHz oscillator (or external clock, if selected) down before it generates the clock for the four programmable timers. The pre-scaler has eight different divider ratios, shown in Table 3-4. Each divider ratio provides a range of intervals to which each of the four timers may be independently programmed. Please note that since there is only one prescaler, all of the timer intervals must lie within the range associated with the selected prescaler value. Table 3-4. Timer Values1 / 16 62.5 kHz 0.032 ms 0.064 ms 0.128 ms 0.256 ms 0.512 ms 1.024 ms 2.048 ms 4.096 ms 0.064 ms 0.128 ms 0.256 ms 0.512 ms 1.024 ms 2.048ms 4.096 ms 8.192 ms 0.128 ms 0.256 ms 0.512 ms 1.024 ms 2.048ms 4.096 ms 8.192 ms 16.384 ms 0.256 ms 0.512 ms 1.024 ms 2.048ms 4.096 ms 8.192 ms 16.384 ms 32.768 ms 0.512 ms 1.024 ms 2.048ms 4.096 ms 8.192 ms 16.384 ms 32.768 ms 65.536 ms 1.024 ms 2.048ms 4.096 ms 8.192 ms 16.384 ms 32.768 ms 65.536 ms 131.072 ms 2.048ms 4.096 ms 8.192 ms 16.384 ms 32.768 ms 65.536 ms 131.072 ms 262.144 ms 4.096 ms 8.192 ms 16.384 ms 32.768 ms 65.536 ms 131.072 ms 262.144 ms 524.288 ms 1. Timer values based on 1MHz clock. / 32 31.2 kHz / 64 15.6 kHz / 128 7.8 kHz / 256 3.9 kHz / 512 2.0 kHz / 1024 1.0 kHz / 2048 0.5 kHz 3-16 Lattice Semiconductor ISPPAC-POWR1208P1 Data Sheet For design entry, the user can select the source for the clock and the PAC-Designer software will calculate the appropriate delays in an easy-to-select menu format. The control inputs for Timer1-Timer4 can be driven by any of the 16 PLD macrocell outputs. The reset for the timers is a function of the Global Reset pin (RESET), a power-on reset or when the timer gate goes low. The waveforms in Figure 3-6 show the basic timer start and reset functions. Timer and clock divider values are entered in during the design phase using PAC-Designer software, simple pull-down menus allow the user to select the clocking mode and the values for the timers and the PLD clock. Figure 3-6. Timer Waveforms Timer Gate (From PLD) Timer Period Timer Period Timer Output (To PLD) Start Timer Timer Expired ProgrammableTimer Delay Reset Timer Start Timer Timer Expired ProgrammableTimer Delay Note that if the clock module is configured as "slave" (i.e. the CLK is an input), the actual time-out of the four timers is determined by the external clock frequency. 3-17 Lattice Semiconductor ISPPAC-POWR1208P1 Data Sheet Master-Slave and PLD Expansion Modes To support designs requiring more I/O or logic resources than those provided by the ISPPAC-POWR1208P1, it is possible to gang a number of devices together, or to add a CPLD to provide additional logic. Figure 3-7 shows an example of slaving a CPLD and two ISPPAC-POWR1208P1's to a single master device Figure 3-7. Example of ISPPAC-POWR1208P1's and CPLD in Expansion Mode V+ RPU V+ RPU RESET CLK CLOCK ispPACPOWR1208P1 Master POR RESET Clock Divider Expansion PLD POR CLK Wired `OR' Connection ispPACPOWR1208P1 Slave RESET RESET POR ispPACPOWR1208P1 Slave CLK In this circuit a 1 MHz CLK output is broadcast from the master device to all of the slave devices. The PLD prescaler should be set identically for both the master and slave ispPAC device to ensure synchronous operation. In the case of the CPLD, some internal logic will need to be used to essentially replicate the function of the ispPAC devices' PLD prescaler to ensure that it also operates synchronously. The POR (power-on reset) signal from the master device is broadcast to all of the slave devices, holding them in a reset state until the master device's power-on-reset sequence completes. Because each of the ispPAC slave devices have their own power-on-reset circuitry, their signals are wire-OR'ed together and fed back into the master device's RESET. This causes all of the devices to remain in a reset state until all power-on-reset sequences have been successfully completed. While it is possible to also slave ispPAC-POWR1208 and ispPAC-POWR604 devices to an ISPPAC-POWR1208P1, the converse is not true. This is because the ispPAC-POWR1208 and 604 devices operate from a 250kHz internal clock, while the ISPPAC-POWR1208P1 requires a 1MHz clock to maintain proper internal operation. Table 3-5 summarizes the requirements for slaving a device to the ISPPAC-POWR1208P1. 3-18 Lattice Semiconductor Table 3-5. ISPPAC-POWR1208P1 Expansion Requirements Slave Device ISPPAC-POWR1208P1 ispPAC-POWR1208 ispPAC-POWR604 CPLD or FPGA Slave Configuration External Clock Mode External Clock Mode ISPPAC-POWR1208P1 Data Sheet Master Configuration Select 1MHz Clock Output Select PLD Prescaler Output Select 1MHz Clock Output Select PLD Prescaler output Clock Prescaler implemented in logic No Clock Prescaler Note that because different slave devices impose different requirements for master clock output frequency, there are limitations on what types of slave devices may be operated synchronously from a single master. For example, it is not generally possible to slave both ISPPAC-POWR1208P1's and ispPAC-POWR1208's (or POWR604's) together to a single ISPPAC-POWR1208P1. Output Configuration Modes The output pins for the ISPPAC-POWR1208P1 device are programmable for different functional modes. The four outputs HVOUT1-HVOUT4, can be used as FET gate drivers or be programmed as open-drain digital outputs. Figure 3-8 explains the details of the gate driver mode. Figure 3-8. Basic Function Diagram for an Output in High-Voltage MOSFET Gate Driver Mode VPP (8-12V) ISource (0.5-50uA) Output to IC Pin 8k Digital In From Sequence Controller Figure 3-8 shows an output programmed for gate driver mode. In this mode the output is a current source that is programmable between 0.5A to 50A. The maximum voltage that the output level at the pin will rise is also programmable. The levels required depend on the gate-to-source threshold of the FET and the supply voltage. The maximum level needs to be sufficient to bias the gate-to-source threshold on and also accommodate the load voltage at the FET's source, since the source pin of the FET is tied to the supply of the target board. When the HVOUT pin is sourcing current, charging a FET gate, the current is programmable between 0.5A and 50A. When the driver is turned to the off state, the driver will sink current to ground through the 8k resistor. 3-19 Lattice Semiconductor ISPPAC-POWR1208P1 Data Sheet Predicting MOSFET Turn-on Time Because the ISPPAC-POWR1208P1's MOSFET output drivers source a precise and well-defined output current, it becomes possible to predict MOSFET gate rise times if one knows the value of the load capacitance presented by the MOSFET being driven. The other method is by relating the total gate charge to the gate-to-source voltage. Figure 3-9. MOSFET Gate Charge vs. Gate-Source Voltage 9 VGS, Gate-to-source Voltage (V) 6.7 6 3 0 0 20 40 60 QG, Total Gate Charge (nC) Using this method, it becomes straightforward to estimate the gate rise time for a given charging current. As an example a MOSFET's source voltage (VS) will be 3.3V when the device is fully switched on, while the gate voltage (VG) will be 10V in this condition. The device's gate-to-source voltage (VGS) will therefore be 6.7V. Reading across and down the plot of Figure 3-9, a VGS of 6.7V corresponds to ~40 nC of gate charge (QG). Because charge is equal to the product of current (I) and time (tCHARGE-TIME) when current is constant, gate charging time can be expressed as: dQ (1) i= dt tCHARGE-TIME = QG I (2) For this example, let us assume a charging current of 10.9A. Gate charging time is given by: tCHARGE-TIME = 40 x 10-9C 10.9 x 10-6A = 3.7 x 10-3s (3) Validation of this result can be seen in the scope plot shown in Figure 3-10. The top set of traces shows gate rise times for various (5.5A to 50.3A) gate drive currents. The trace labeled 10.9A shows gate voltage VG rising from 0V to 10V in slightly over 3 milliseconds, which agrees to within 25% of our predicted value, well within the limits of device-to-device variation. 3-20 Lattice Semiconductor ISPPAC-POWR1208P1 Data Sheet Figure 3-10. Gate and Source Voltage Responses for a 3.3V Supply MOSFET gate capacitance ranges from hundreds to thousands of picoFarads. Refer to the MOSFET manufacturer's data sheet for values of Cgs (Capacitance gate-to-source). If slower ramps are required, an additional external low leakage capacitor (e.g. a polycarbonate or other poly type capacitor) can be added from the gate to ground. As a good design practice, it is recommended that a series resistor of 10-100 be placed in the gate drive signal near the FET gate pin to reduce the possibility that the FET may self-oscillate. Charge Pump Four internal charge pumps are provided to fully support external N-channel FET devices. No external components are required for the charge pumps. The output voltage is programmable from 8 to 12V in 0.5V steps. The user must select a high voltage limit no greater than 7.5V above VDD (the software assists this process). This voltage is controlled with an on-chip feedback loop, and is independent of the actual supply voltage. Programmable Output Voltage Levels for HVOUT1- HVOUT4 There are eight selectable steps for the output voltage of the FET drivers when in FET driver mode. The output pins HVOUT1-4 are current source outputs, each with a programmable current. The current is programmable in 32 different steps ranging from 0.5A to 50A. The voltage that the pin is capable of driving to is listed in Table 3-6. For each supply range, the charge-pump range will be set by the software. Table 3-6. HVOUT Gate Driver Voltage Range VDD = 3.3V 8 8.5 9 9.5 10 VDD = 5V 8 8.5 9 9.5 10 10.5 11 12 3-21 Lattice Semiconductor ISPPAC-POWR1208P1 Data Sheet IEEE Standard 1149.1 Interface Communication with the ISPPAC-POWR1208P1 is facilitated via an IEEE 1149.1 test access port (TAP). It is used by the ISPPAC-POWR1208P1 as a serial programming interface, and not for boundary scan test purposes. There are no boundary scan logic registers in the ISPPAC-POWR1208P1 architecture. This does not prevent the ispPACPOWR1208P1 from functioning correctly, however, when placed in a valid serial chain with other IEEE 1149.1 compliant devices. Since the ISPPAC-POWR1208P1 is used to powerup other devices, it should be programmed in a separate chain from PLDs, FPGAs or other JTAG devices. A brief description of the ISPPAC-POWR1208P1 serial interface follows. For complete details of the reference specification, refer to the publication, Standard Test Access Port and Boundary-Scan Architecture, IEEE Std 1149.11990 (which now includes IEEE Std 1149.1a-1993). Overview An IEEE 1149.1 test access port (TAP) provides the control interface for serially accessing the digital I/O of the ISPPAC-POWR1208P1. The TAP controller is a state machine driven with mode and clock inputs. Under the correct protocol, instructions are shifted into an instruction register, which then determines subsequent data input, data output, and related operations. Device programming is performed by addressing various registers, shifting data in, and then executing the respective program instruction. The programming instructions transfer the data into internal E2CMOS memory. It is these non-volatile memory cells that determine the configuration of the ispPACPOWR1208P1. By cycling the TAP controller through the necessary states, data can also be shifted out of the various registers to verify the current ISPPAC-POWR1208P1 configuration. Instructions exist to access all data registers and perform internal control operations. For compatibility between compliant devices, two data registers are mandated by the IEEE 1149.1 specification. Other registers are functionally specified, but inclusion is strictly optional. Finally, there are provisions for optional user data registers that are defined by the manufacturer. The two required registers are the bypass and boundaryscan registers. For ISPPAC-POWR1208P1, the bypass register is a 1-bit shift register that provides a short path through the device when boundary testing or other operations are not being performed. The ispPACPOWR1208P1, as mentioned earlier has no boundary-scan logic and therefore no boundary scan register. All instructions relating to boundary scan operations place the ISPPAC-POWR1208P1 in the BYPASS mode to maintain compliance with the specification. The optional identification (IDCODE) register described in IEEE 1149.1 is also included in the ispPACPOWR1208P1. Six additional user data registers are included in the TAP of the ISPPAC-POWR1208P1 as shown in Figure 3-11. Most of these additional registers are used to program and verify the analog configuration (CFG) and PLD bits. A status register is also provided to read the status of the twelve analog comparators. 3-22 Lattice Semiconductor Figure 3-11. TAP Registers ANALOG COMPARATOR ARRAY (12 bits) ISPPAC-POWR1208P1 Data Sheet STATUS REGISTER (12 bits) IDCODE REGISTER (32 bits) UES REGISTER (16 bits) CFG REGISTER (41 bits) CFG ADDRESS REGISTER (4 bits) MULTIPLEXER ANALOG CONFIGURATION E2 NON-VOLATILE MEMORY (164 bits) PLD DATA REGISTER (81 bits) PLD ADDRESS REGISTER (75 bits) PLD AND / ARCH E2 NON-VOLATILE MEMORY (6075 bits) INSTRUCTION REGISTER (6 bits) BYPASS REGISTER (1 bit) TEST ACCESS PORT (TAP) LOGIC OUTPUT LATCH TDI TCK TMS TDO TAP Controller Specifics The TAP is controlled by the Test Clock (TCK) and Test Mode Select (TMS) inputs. These inputs determine whether an Instruction Register or Data Register operation is performed. Driven by the TCK input, the TAP consists of a small 16-state controller. In a given state, the controller responds according to the level on the TMS input as shown in Figure 3-12. Test Data In (TDI) and TMS are latched on the rising edge of TCK, with Test Data Out (TDO) becoming valid on the falling edge of TCK. There are six steady states within the controller: Test-Logic-Reset, Run-Test/ Idle, Shift-Data-Register, Pause-Data-Register, Shift-Instruction-Register, and Pause-Instruction-Register. But there is only one steady state for the condition when TMS is set high: the Test-Logic-Reset state. This allows a reset of the test logic within five TCKs or less by keeping the TMS input high. Test-Logic-Reset is the power-on default state. When the correct logic sequence is applied to the TMS and TCK inputs, the TAP will exit the Test-Logic-Reset state and move to the desired state. The next state after Test-Logic-Reset is Run-Test/Idle. Until a data or instruction scan is performed, no action will occur in Run-Test/Idle (steady state = idle). After Run-Test/Idle, either a data or instruction scan is performed. The states of the Data and Instruction Register blocks are identical to each other differing only in their entry points. When either block is entered, the first action is a capture operation. For the Data Registers, the Capture-DR state is very simple; it captures (parallel loads) data onto the selected serial data path (previously chosen with the appropriate instruction). For the Instruction Register, the Capture-IR state will always load the IDCODE instruction. It will always enable the ID Register for readout if no other instruction is loaded prior to a Shift-DR operation. This, in conjunction with mandated bit codes, allows a "blind" interrogation of any device in a compliant IEEE 1149.1 serial chain. 3-23 Lattice Semiconductor Figure 3-12. TAP States 1 Test-Logic-Reset 0 1 0 Run-Test/Idle ISPPAC-POWR1208P1 Data Sheet Select-DR-Scan 0 1 Capture-DR 0 Shift-DR 0 1 Exit1-DR 1 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 0 1 1 Select-IR-Scan 0 1 Capture-IR 0 Shift-IR 0 1 Exit1-IR 1 0 Pause-IR 1 0 Exit2-IR 1 Update-IR 1 0 0 Note: The value shown adjacent to each state transition represents the signal present at TMS at the time of a rising edge at TCK. From the Capture state, the TAP transitions to either the Shift or Exit1 state. Normally the Shift state follows the Capture state so that test data or status information can be shifted out or new data shifted in. Following the Shift state, the TAP either returns to the Run-Test/Idle state via the Exit1 and Update states or enters the Pause state via Exit1. The Pause state is used to temporarily suspend the shifting of data through either the Data or Instruction Register while an external operation is performed. From the Pause state, shifting can resume by re-entering the Shift state via the Exit2 state or be terminated by entering the Run-Test/Idle state via the Exit2 and Update states. If the proper instruction is shifted in during a Shift-IR operation, the next entry into Run-Test/Idle initiates the test mode (steady state = test). This is when the device is actually programmed, erased or verified. All other instructions are executed in the Update state. Test Instructions Like data registers, the IEEE 1149.1 standard also mandates the inclusion of certain instructions. It outlines the function of three required and six optional instructions. Any additional instructions are left exclusively for the manufacturer to determine. The instruction word length is not mandated other than to be a minimum of two bits, with only the BYPASS and EXTEST instruction code patterns being specifically called out (all ones and all zeroes respectively). The ISPPAC-POWR1208P1 contains the required minimum instruction set as well as one from the optional instruction set. In addition, there are several proprietary instructions that allow the device to be configured, verified, and monitored. For ISPPAC-POWR1208P1, the instruction word length is 6-bits. All ISPPAC-POWR1208P1 instructions available to users are shown in Table 3-7. 3-24 Lattice Semiconductor Table 3-7. ISPPAC-POWR1208P1 TAP Instruction Table Instruction EXTEST ADDPLD1 DATAPLD1 ERASEAND1, 2 ERASEARCH PROGPLD1, 2 PROGESF1, 2 BYPASS READPLD ADDCFG 1 1 1 1, 2 ISPPAC-POWR1208P1 Data Sheet Code 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 Description External Test. Defaults to BYPASS. Address PLD address register (75 bits). Address PLD column data register (81 bits). Bulk Erase AND array. Bulk Erase Architect array. Program PLD column data register into E2. Program the Electronic Security Fuse bit. Bypass (connect TDI to TDO). Reads PLD column data from E2 to the register (81 bits). Fast VPP discharge. Address CFG array address (4 bits). Address CFG data (41 bits). Bulk Erase CFG data. Program CFG data register into E2. Read CFG column data from E2 to the register (41 bits). Bulk Erase all E2 memory (CFG, PLD, USE, and ESF). Digital outputs hiZ (FET pulled L) Enable program mode (SAFESTATE IO) Address Identification Code data register (32 bits). Disable Program mode (normal IO) Address STATUS register (12 bits). Sample/Preload. Default to Bypass. Bulk Erase UES. Reads UES data from E2 and selects the UES register (16 bits). Program UES data register into E2. Bypass (connect TDI to TDO). DISCHARGE DATACFG1 ERASECFG READCFG1 CFGBE 1, 2 1, 2 001100 001101 001110 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 1xxxxx PROGCFG1, 2 SAFESTATE1 PROGRAMEN1 IDCODE PROGRAMDIS ADDSTATUS SAMPLE ERASEUES1, 2 SHIFTUES PROGUES1, 2 BYPASS 1. When these instructions are executed, the outputs are placed in the same mode as the instruction SAFESTATE (as described later) to prevent invalid and potentially destructive power supply sequencing. 2. Instructions that erase or program the E2CMOS memory must be executed only when the supply to the device is maintained at 3.0V to 5.5V. BYPASS is one of the three required instructions. It selects the Bypass Register to be connected between TDI and TDO and allows serial data to be transferred through the device without affecting the operation of the ispPACPOWR1208P1. The IEEE 1149.1 standard defines the bit code of this instruction to be all ones (111111). The required SAMPLE/PRELOAD instruction dictates the Boundary-Scan Register be connected between TDI and TDO. The ISPPAC-POWR1208P1 has no boundary scan register, so for compatibility it defaults to the BYPASS mode whenever this instruction is received. The bit code for this instruction is defined by Lattice as shown in Table 3-7. The EXTEST (external test) instruction is required and would normally place the device into an external boundary test mode while also enabling the boundary scan register to be connected between TDI and TDO. Again, since the ISPPAC-POWR1208P1 has no boundary scan logic, the device is put in the BYPASS mode to ensure specification compatibility. The bit code of this instruction is defined by the 1149.1 standard to be all zeros (000000). The optional IDCODE (identification code) instruction is incorporated in the ISPPAC-POWR1208P1 and leaves it in its functional mode when executed. It selects the Device Identification Register to be connected between TDI and TDO. The Identification Register is a 32-bit shift register containing information regarding the IC manufacturer, 3-25 Lattice Semiconductor ISPPAC-POWR1208P1 Data Sheet device type and version code (Figure 3-13). Access to the Identification Register is immediately available, via a TAP data scan operation, after power-up of the device, or by issuing a Test-Logic-Reset instruction. The bit code for this instruction is defined by Lattice as shown in Table 3-7. Figure 3-13. ID Code MSB LSB XXXX / 0000 0001 0100 0010 / 0000 0100 001 / 1 Part Number (16 bits) 0142h = ISPPAC-POWR1208P1 Version (4 bits) E 2 Configured JEDEC Manufacturer Identity Code for Lattice Semiconductor (11 bits) Constant 1 (1 bit) per 1149.1-1990 ISPPAC-POWR1208P1 Specific Instructions There are 21 unique instructions specified by Lattice for the ISPPAC-POWR1208P1. These instructions are primarily used to interface to the various user registers and the E2CMOS non-volatile memory. Additional instructions are used to control or monitor other features of the device. A brief description of each unique instruction is provided in detail below, and the bit codes are found in Table 3-7. ADDPLD - This instruction is used to set the address of the PLD AND/ARCH arrays for subsequent program or read operations. This instruction also forces the outputs into the SAFESTATE. DATAPLD - This instruction is used to shift PLD data into the register prior to programming or reading. This instruction also forces the outputs into the SAFESTATE. ERASEAND - This instruction will bulk erase the PLD AND array. The action occurs at the second rising edge of TCK in Run-Test-Idle JTAG state. The device must already be in programming mode (PROGRAMEN instruction). This instruction also forces the outputs into the SAFESTATE. ERASEARCH - This instruction will bulk erase the PLD ARCH array. The action occurs at the second rising edge of TCK in Run-Test-Idle JTAG state. The device must already be in programming mode (PROGRAMEN instruction). This instruction also forces the outputs into the SAFESTATE. PROGPLD - This instruction programs the selected PLD AND/ARCH array column. The specific column is preselected by using ADDPLD instruction. The programming occurs at the second rising edge of the TCK in Run-TestIdle JTAG state. The device must already be in programming mode (PROGRAMEN instruction). This instruction also forces the outputs into the SAFESTATE. PROGESF - This instruction is used to program the electronic security fuse (ESF) bit. Programming the ESF bit protects proprietary designs from being read out. The programming occurs at the second rising edge of the TCK in Run-Test-Idle JTAG state. The device must already be in programming mode (PROGRAMEN instruction). This instruction also forces the outputs into the SAFESTATE. READPLD - This instruction is used to read the content of the selected PLD AND/ARCH array column. This specific column is preselected by using ADDPLD instruction. This instruction also forces the outputs into the SAFESTATE. DISCHARGE - This instruction is used to discharge the internal programming supply voltage after an erase or programming cycle and prepares ISPPAC-POWR1208P1 for a read cycle. This instruction also forces the outputs into the SAFESTATE. 3-26 Lattice Semiconductor ISPPAC-POWR1208P1 Data Sheet ADDCFG - This instruction is used to set the address of the CFG array for subsequent program or read operations. This instruction also forces the outputs into the SAFESTATE. DATACFG - This instruction is used to shift data into the CFG register prior to programming or reading. This instruction also forces the outputs into the SAFESTATE. ERASECFG - This instruction will bulk erase the CFG array. The action occurs at the second rising edge of TCK in Run-Test-Idle JTAG state. The device must already be in programming mode (PROGRAMEN instruction). This instruction also forces the outputs into the SAFESTATE. PROGCFG - This instruction programs the selected CFG array column. This specific column is preselected by using ADDCFG instruction. The programming occurs at the second rising edge of the TCK in Run-Test-Idle JTAG state. The device must already be in programming mode (PROGRAMEN instruction). This instruction also forces the outputs into the SAFESTATE. READCFG - This instruction is used to read the content of the selected CFG array column. This specific column is preselected by using ADDCFG instruction. This instruction also forces the outputs into the SAFESTATE. CFGBE - This instruction will bulk erase all E2CMOS bits (CFG, PLD, UES, and ESF) in the ispPACPOWR1208P1. The device must already be in programming mode (PROGRAMEN instruction). This instruction also forces the outputs into the SAFESTATE. SAFESTATE - This instruction turns off all of the open-drain output transistors. Pins that are programmed as FET drivers will be placed in the active low state. This instruction is effective after Update-Instruction-Register JTAG state. PROGRAMEN - This instruction enables the programming mode of the ISPPAC-POWR1208P1. This instruction also forces the outputs into the SAFESTATE. IDCODE - This instruction connects the output of the Identification Code Data Shift (IDCODE) Register to TDO (Figure 3-14), to support reading out the identification code. Figure 3-14. IDCODE Register TDO Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PROGRAMDIS - This instruction disables the programming mode of the ISPPAC-POWR1208P1. The Test-LogicReset JTAG state can also be used to cancel the programming mode of the ISPPAC-POWR1208P1. ADDSTATUS - This instruction is used to both connect the status register to TDO (Figure 3-15) and latch the 12 voltage monitor (comparator outputs) into the status register. Latching of the 12 comparator outputs into the status register occurs during Capture-Data-Register JTAG state. Figure 3-15. Status Register TDO VMON 1 VMON 2 VMON 3 VMON 4 VMON 5 VMON 6 VMON 7 VMON 8 VMON 9 VMON 10 VMON 11 VMON 12 ERASEUES - This instruction will bulk erase the content of the UES E2CMOS memory. The device must already be in programming mode (PROGRAMEN instruction). This instruction also forces the outputs into the SAFESTATE. SHIFTUES - This instruction both reads the E2CMOS bits into the UES register and places the UES register between the TDI and TDO pins (as shown in Figure U), to support programming or reading of the user electronic signature bits. 3-27 Lattice Semiconductor Figure 3-16. UES Register ISPPAC-POWR1208P1 Data Sheet TDO Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PROGUES - This instruction will program the content of the UES Register into the UES E2CMOS memory. The device must already be in programming mode (PROGRAMEN instruction). This instruction also forces the outputs into the SAFESTATE. Notes: In all of the descriptions above, SAFESTATE refers both to the instruction and the state of the digital output pins, in which the open-drains are tri-stated and the FET drivers are pulled low. Before any of the above programming instructions are executed, the respective E2CMOS bits need to be erased using the corresponding erase instruction. Application Example The ISPPAC-POWR1208P1 device has 12 comparators to monitor various power supply levels. The comparators each have a programmable trip point that is programmed by the user at design time. The output of the comparators are latched and optionally filtered before being fed into the PLD logic array to drive the state machine logic or monitor logic. The comparator's filtered outputs COMP1...COMP8 are also routed to external pins to be monitored directly or can be used to drive additional control logic if expansion is required. The comparator outputs are opendrain type output buffers and require a pull up resistor to drive a logic high. All 12 comparators have hysteresis, the hysteresis is dependent on the voltage trip point scale that is set, it ranges from 4mV for a 0.680V trip point to 30mV for a 5.93V trip point. The comparators can be set with a trip point from 0.68V to 5.93V, with 384 different values. The application diagram shows a set-up that can monitor and control multiple power supplies. The ispPACPOWR1208P1 device controls FET switches to ramp the supplies at different slew rates and time delays. The digital outputs and inputs are also used to interface with the board that is being powered up. To reduce the possibility of RF oscillation, a gate resistor (RG) is often inserted in series with the gate of the MOSFET power switch. This resistor should be placed physically close to the MOSFET gate terminal, and connected by as short a PCB trace as is feasible. An appropriate value for these gate resistors is highly dependent on both the characteristics of the MOSFET being used and the circumstances of the application, but will often be in the range of 10 to 100. 3-28 Lattice Semiconductor ISPPAC-POWR1208P1 Data Sheet Figure 3-17. Typical Application Example: ISPPAC-POWR1208P1 Driving [4] FET Switches [4] Digital OE/EN Lines Primary + - DC/DC + Supply Gnd +5V RG +3.3V +5V Circuits Primary + - + DC/DC Supply Gnd +3.3V Circuits RG Primary + - + DC/DC Supply Gnd +2.5V RG +2.5V Circuits Primary + - + DC/DC Supply Gnd +1.0V RG +1V Circuits 12 Analog Inputs 10uF VDD VDDINP VMON1 HVOUT1 VMON2 HVOUT2 VMON3 HVOUT3 VMON4 HVOUT4 VMON5 OUT5 VMON6 ISPPAC-POWR1208P1 OUT6 VMON7 OUT7 VMON8 OUT8 Power Sequence VMON9 Comp1 Controller VMON10 Comp2 VMON11 Comp3 VMON12 Comp4 CLK Comp5 Comp6 RESET Comp7 IN1 Comp8 IN2 POR 0.1uF OE/EN DC/DC Supply or Regulator OE/EN VDD DC/DC Supply or Regulator 3.3V EN 3.3V EN 0.1uF Digital Logic IN3 IN4 CREF Digital Logic 3-29 Lattice Semiconductor ISPPAC-POWR1208P1 Data Sheet Software-Based Design Environment Design Entry Software All functions within the ISPPAC-POWR1208P1 are controlled through a Windows-based software development tool called PAC-Designer. PAC-Designer is an easy-to-use graphical user interface (Figure 3-18) that allows the user to set up the ISPPAC-POWR1208P1 to perform given functions, such as timed sequences for power supply and monitor trip points for the voltage monitor inputs. The software tool gives the user control over how the device drives the outputs and the functional configurations for all I/O pins. User-friendly dialog boxes are provided to set and edit all of the analog features of the ISPPAC-POWR1208P1. An extension to the schematic screen is the LogiBuilder design environment (Figure 3-19) that is used to enter and edit control sequences. Again, user-friendly dialog boxes are provided in this window to help the designer to quickly implement sequences that take advantage of the powerful built-in PLD. Once the configurations are chosen and the sequence has been described by the utilities, the device is ready to program. A standard JTAG interface is used to program the E2CMOS memory. PAC-Designer software supports downloading the device through the PC's parallel port. The ISPPAC-POWR1208P1 can be reprogrammed using the software and ispDOWNLOAD(R) Cable assembly, to adjust for variations in supply timing, sequencing or scaling of voltage monitor inputs. Figure 3-18. PAC-Designer Schematic Screen The user interface (Figure 3-18) provides access to various internal function blocks within the ispPACPOWR1208P1 device. Analog Inputs: Accesses the programmable threshold trip-points for the comparators and pin naming conventions. Digital Inputs: Digital input naming configurations and digital inputs feed into the internal PLD for the sequence controller. Sequence Controller: Incorporates a PLD architecture for designing the state machine to control the order and functions associated with the user-defined power-up sequence/monitor and control. 3-30 Lattice Semiconductor ISPPAC-POWR1208P1 Data Sheet FET Drivers: Allows the user to define ramp rates by controlling the current driven to the gate of the external FETs. Maximum voltage levels and pin names are also set using this functional block. The four FET driver outputs HVOUT1-4 can also be configured as open-drain digital logic outputs. Logic Outputs: These pins are configured and assigned in the Logic Output Functional Block. The four digital outputs are open-drain and require a pull-up resistor. Internal Clock: The internal clock configuration and clock prescaler values are user-programmable, as well as the four internal programmable timers used for sequence delay. User Electronic Signature (UES): Stores 16 bits of ID or board information in non-volatile E2CMOS. Figure 3-19. PAC-Designer LogiBuilder Screen Programming of the ISPPAC-POWR1208P1 is accomplished using the Lattice ispDOWNLOAD Cable. This cable connects to the parallel port of a PC and is driven through the PAC-Designer software. The software controls the JTAG TAP interface and shifts in the JEDEC data bits that set the configuration of all the analog and digital circuitry that the user has defined during the design process. Power to the device must be set at 3.0V to 5.5V during programming, once the programming steps have been completed, the power supply to the ISPPAC-POWR1208P1 can be set from 2.7V to 5.5V. Once programmed, the onchip non-volatile E2CMOS bits hold the entire design configuration for the digital circuits, analog circuits and trip points for comparators etc. Upon powering the device up, the non-volatile E2CMOS bits control the device configuration. If design changes need to be made such as adjusting comparator trip points or changes to the digital logic functions, the device is simply re-programmed using the ispDOWNLOAD Cable. Design Simulation Capability Support for functional simulation of the control sequence is provided using the software tools Waveform Editor and Waveform Viewer. Both applications are spawned from the LogiBuilder environment of PAC-Designer. The simulation engine combines the design file with a stimulus file (edited by the user with Waveform Editor) to produce an output file that can be observed with the Waveform Viewer (Figure 3-20). 3-31 Lattice Semiconductor Figure 3-20. PAC-Designer Functional Simulation Screen ISPPAC-POWR1208P1 Data Sheet In-System Programming The ISPPAC-POWR1208P1 is an in-system programmable device. This is accomplished by integrating all E2CMOS configuration memory and control logic on-chip. Programming is performed through a 4-wire, IEEE 1149.1 compliant serial JTAG interface. Once a device is programmed, all configuration information is stored on-chip, in non-volatile E2CMOS memory cells. The specifics of the IEEE 1149.1 serial interface and all ISPPAC-POWR1208P1 instructions are described in the JTAG interface section of this data sheet. User Electronic Signature The User Electronic Signature (UES), allows the designer to include identification bits or serial numbers inside the device, stored in E2CMOS memory. The ISPPAC-POWR1208P1 contains 16 UES bits that can be configured by the user to store unique data such as ID codes, revision numbers or inventory control codes. Electronic Security An Electronic Security Fuse (ESF) bit is provided to prevent unauthorized readout of the E2CMOS bit pattern. Once programmed, this cell prevents further access to the functional user bits in the device. This cell can only be erased by reprogramming the device; this way the original configuration cannot be examined or copied once programmed. Usage of this feature is optional. Production Programming Support Once a final configuration is determined, an ASCII format JEDEC file can be created using the PAC-Designer software. Devices can then be ordered through the usual supply channels with the user's specific configuration already preloaded into the devices. By virtue of its standard interface, compatibility is maintained with existing production programming equipment, giving customers a wide degree of freedom and flexibility in production planning. Part Number PAC-SYSPOWR1208P1 PACPOWR1208P1-EV Description Complete system kit, evaluation board, ispDOWNLOAD Cable and software Evaluation board only, with components, fully assembled Evaluation Fixture The ISPPAC-POWR1208P1 Design Kit includes an engineering prototype board that can be connected to the parallel port of a PC using a Lattice ispDOWNLOAD cable. It demonstrates proper layout techniques for the ispPACPOWR1208P1 and can be used in real time to check circuit operation as part of the design process. LEDs are supplied to debug designs without involving test equipment. Input and output connections as well as a "breadboard" circuit area are provided to speed debugging of the circuit. The board includes an area for prototyping other circuits and interconnect areas with pads for pins or cables. The user can check out designs on the hardware and make necessary changes to the design for the function required. 3-32 Lattice Semiconductor ISPPAC-POWR1208P1 Data Sheet Package Diagrams 44-Pin TQFP (Dimensions in Millimeters) PIN 1 INDICATOR 0.20 C A-B D D 44X e 8 TOP VIEW 0.20 M C A-B c NOTES: 1. 2. 3. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5 - 1982. ALL DIMENSIONS ARE IN MILLIMETERS. D DATUMS A, B AND D TO BE DETERMINED AT DATUM PLANE H. D1 DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTRUSION IS 0.254 MM ON D1 AND E1 DIMENSIONS. E E1 L N 0.45 10.00 BSC 12.00 BSC 10.00 BSC 0.60 44 0.80 BSC 0.30 0.30 0.09 0.09 0.37 0.35 0.15 0.13 0.45 0.40 0.20 0.16 0.75 12.00 BSC 5. THE TOP OF PACKAGE MAY BE SMALLER THAN THE BOTTOM OF THE PACKAGE BY 0.15 MM. 6. SECTION B-B: THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 AND 0.25 MM FROM THE LEAD TIP. A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT ON THE PACKAGE BODY. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 7. 8. 3 A E B 3 E1 D 3 4X 0.20 H A-B D D1 BOTTOM VIEW SIDE VIEW SEE DETAIL 'A' b D SEATING PLANE C H A A2 B GAUGE PLANE 0.25 b LEAD FINISH 0.10 C c1 A1 0.20 MIN. B 0-7 L 1.00 REF. b DETAIL 'A' 1 BASE METAL SECTION B-B SYMBOL A A1 A2 MIN. 0.05 1.35 NOM. 1.40 MAX. 1.60 0.15 1.45 e b b1 c c1 3-33 Lattice Semiconductor ISPPAC-POWR1208P1 Data Sheet Part Number Description ISPPAC-POWR1208P1 - 01XX44X Device Family Device Number Operating Temperature Range I = Industrial (-40C to +85C) Package T = 44-pin TQFP TN = Lead-Free 44-pin TQFP* Performance Grade 01 = Standard *Contact factory for package availability. ISPPAC-POWR1208P1 Ordering Information Industrial Part Number ISPPAC-POWR1208P1-01T44I Package TQFP Pins 44 Lead-Free Industrial Part Number ISPPAC-POWR1208P1-01TN44I Package Lead-free TQFP Pins 44 Package Options VMON12 VMON11 VMON10 VMON9 VMON8 CREF VMON7 VMON6 VMON5 VMON4 VMON3 44 37 36 43 42 41 40 39 38 35 HVOUT4 HVOUT3 HVOUT2 HVOUT1 VDD IN1 IN2 IN3 IN4 RESET VDDINP 34 1 2 3 4 5 6 7 8 9 10 11 ISPPAC-POWR1208P1 28 44-pin TQFP 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 33 32 31 30 29 VMON2 VMON1 TMS TDI TRST TDO GND CLK POR TCK COMP1 COMP2 COMP3 COMP4 COMP5 COMP6 COMP7 COMP8 OUT8 OUT7 OUT6 OUT5 Revision History Date February 2005 Version 01.0 Initial release. Change Summary 3-34 |
Price & Availability of ISPPAC-POWR1208P1
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |